Sample Technology Paper on Parity check codes and ECC memories

Parity check codes and ECC memories

Some of the currently existing memories are Random Access Memory (RAM), Static RAM, Dynamic RAM, Read Only Memory (ROM), Erasable Programmable ROM, Masked ROM, Electronically Erasable Programmable ROM, direct access memory and serial access memory. Most of this memories use error-correcting methods while performing READ or WRITE operations (“Memory Devices”). When transmitting information from one point to another digitally like in computer systems, the data might get distorted due to noise along the transmitting channels. This raises the need to come up with error detection and correction techniques to ensure that data is transmitted and received reliably. The primary reason for taking this error detection and correction measures is to make sure that the intended information reaches the recipient. Therefore, the error should not reach a given threshold level.

In digital systems, extra bits are added to the binary code information to detect and correct any error that occurs due to distortion during storage and processing of data in a digital system. The additional bits are referred to as redundant code since they do not hold any significance information and are discarded at the receiver (Maini, 2007). Even though the redundant codes are important in ensuring reliable transmission of information, they introduce some inefficiency in the system.  There are several codes for error detecting and correcting which include Hamming code, repetition code, parity codes and cyclic redundancy check code.

The parity code error detection and correction involves the addition of a single bit that is a ‘1’ or a’0’ to a stream of binary code. Hence making the number of’1s’ in the binary code odd or even including the added bit. Therefore, there are two types of parity code that is even and odd parity code. For example, if o1000001 is the binary information code it can be added a ‘0’ at the beginning to be even parity code (001000001). To generate odd parity for the same a ‘1’ can be added to get 101000001. At the receiver, the number of ‘1s’ is counted giving an odd number for odd parity code and even number for even parity code. Unless this is the case, the receiver detects the presence of an error and to correct it send a request for retransmission until the correct data is received. All these happen in a short period unrecognizable to human users; in fact it is in nanoseconds.  Parity code has two limitations firstly; it cannot detect error when an even number of bits in the binary code is distorted. Secondly, it cannot identify the exact bit with error even after detecting there is an error. The parity code is used in computer systems such as LAN, W-LAN and Wireless Fidelity (Razavi, 2001).  ECC memories are utilized in the transfer of information between the various processing units within a computer system.

Cyclic redundancy check code allows a reasonable level of protection using reduced redundancy. Some step-by-step division obtains the error checking code where the dividend is equal to n+1 and n is the number of bits in the cyclic code. At the receiver, the word received is divided by the divisor to give a zero remainder.  If a non-zero remainder is obtained, definitely, there is an error in the transmitted information and appropriate corrective measures are taken.

In conclusion, it can be observed that all these error detecting and correcting code have advantages and disadvantages. Therefore, while designing a system, they should all be considered and the most efficient and viable for a particular situation chosen.

Work cited

Razavi, Behzad. Design Of Analogue CMOS Intergated Circuit. London: Mc Graw-Hill International, 2001. Print.

“Memory Devices”. N.p., 2016. Web. 10 Mar. 2016.

Maini, Anil k. Digital Electronic: Principle Devices And Applications. West Sussex: John Wiley & Sons Ltd, 2007. Print.